With shrinking transistor dimensions into nano meter scale, electrical parameters of transistors become more sensitive against statistical or random variations. Moreover, accurate estimation of these variations using “atomistic simulators” is time consuming and not a co More
With shrinking transistor dimensions into nano meter scale, electrical parameters of transistors become more sensitive against statistical or random variations. Moreover, accurate estimation of these variations using “atomistic simulators” is time consuming and not a cost effective approach. In this paper for the first time, analytical models have been used to study the impacts of statistical variability of fabrication process on propagation delay time in a 35 nm CMOS NAND gate. With selecting appropriate set from analytical model’s parameters, the impact of statistical variability on the propagation delay time have been modeled and extended. Moreover, target analytical model has been benchmarked against statistical variability of fabrication process. The results obtained from extension of this model have been compared with the accurate atomistic simulations. It is observed that by applying different sets of parameters the maximum error of propagation delay time reaches to 8.7% against accurate atomistic simulations but by applying our proposed approach, Standard Deviation (SD) error of propagation delay is estimated to 2.4%. Also the SD error of propagation delay reaches to 9.9% when normal regenerated parameters have been used. Eventually using proposed algorithm which encompasses regenerated Gaussian parameters while taking the correlation factor into account, the SD error decreases to 1.6%.
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With advancement of integrated circuit technology and aggressive scaling into nanometer regime, statistical variability in device electrical characteristics caused by discreteness of charge and fabrication process variations has significantly increased. These variations More
With advancement of integrated circuit technology and aggressive scaling into nanometer regime, statistical variability in device electrical characteristics caused by discreteness of charge and fabrication process variations has significantly increased. These variations in turn result in fluctuations in output characteristics of important analog building blocks and in particular, amplifiers. In this paper, with the aid of Monte-Carlo simulations for a transconductance amplifier and using 1000 different compact models of MOSFET transistors in 35nm technology node, statistical variations of important circuit parameters are investigated and analyzed based on their statistical distributions. Moreover, statistical correlations between circuit parameters are extracted. Analysis of statistical variations for circuit parameters and their correlations has a direct impact on reduction of cost and time of a design and thus, is of great amount of significance.
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Nowadays, analog to digital (A/D) converters are indistinguishable parts of system on chip (soC) structures because they omit the distance between analog real data and digital logic world. Due to this fact and ever increasing trend for using portable instruments, the fi More
Nowadays, analog to digital (A/D) converters are indistinguishable parts of system on chip (soC) structures because they omit the distance between analog real data and digital logic world. Due to this fact and ever increasing trend for using portable instruments, the figures of merit for design of these converters such as speed, power and occupied area are improved. Different methods are proposed to improve the performance of these converters. In this paper, we design a fast and low power ADC using carbon nano-tube field effect transistor (CNTFET) and then its performance is comprehensively compared with a MOSFET based counterpart at the same technology node. The performance is studied two encoders: ROM and Fat tree. The obtained results are presented using HSPICE simulator at 0.9 V power supply. The simulated data from CNTFET based converter shows significant improvements in delay and power compared with its CMOS based counterpart. The power and delay obtained from CNTFET based converter using ROM encoder are improved by 92.5% and 54% with respect to the same parameters obtained from CMOS based design while the improvements using a Fat tree encoder in CNTFET converter reaches 93% and 72% in comparison with CMOS conventional design.
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A single electron transistor is a nanoscale device comprised of three metallic electrodes and one island or quantum dot. The island can made of carbon nano materials like a graphene nanoribbon. The number of carbon atoms along the width of the graphene nanoribbon affect More
A single electron transistor is a nanoscale device comprised of three metallic electrodes and one island or quantum dot. The island can made of carbon nano materials like a graphene nanoribbon. The number of carbon atoms along the width of the graphene nanoribbon affect on the speed of transistor operation and coulomb blockade region. In this research, the current for a single electron transistor utilizing a graphene nanoribbon island is modeled. The impact of several parameters on the transistor current is investigated including the number of carbon atoms along the width, length of nanoribbon, and the applied gate voltage. The modeling results show that increasing the number of carbon atoms along the width of the nanoribbon results in reduced coulomb blockade region. Moreover, reducing the length of nanoribbon and increasing the applied gate voltage cause a decrease in the zero current range of the transistor. Increasing the number of atoms along the width of three islands also gives a boost in the electron tunneling region and thus, the transistor performance will be improved.
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