Combination of 3D stacking and network-on-chip (NoC), known as 3D NoC, has several advantages such as reduced propagation delay, chip area and interconnect, and power consumption, and bandwidth increase. Despite these advantages, 3D stacking causes the increased power d
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Combination of 3D stacking and network-on-chip (NoC), known as 3D NoC, has several advantages such as reduced propagation delay, chip area and interconnect, and power consumption, and bandwidth increase. Despite these advantages, 3D stacking causes the increased power density per chip area and subsequently increases the chip temperature. Temperature increase causes performance degradation and reliability reduction. Therefore, design of temperature management algorithms is essential for these systems. In this paper, we propose a task migration scheme for thermal management of 3D NoCs. The process of migration destinations for hot spots is an NP-complete problem which can be solved by using heuristic algorithms. To this end, we utilize a simulated annealing method in our algorithm. We consider migration overhead in addition to the temperature of the processing elements in migration destination selection process. Simulation results indicate up to 28 percentage peak temperature reduction, on average, for the benchmark that has the largest number of tasks. The proposed scheme has low migration overhead.
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