Three-Dimensional Chips are made of stacking silicon layers which communicate with each other by Through-Silicon-Via (TSV) links. Manufacturing cost of Three-Dimensional chips is a function of the number of TSVs because the fabricating of a three-dimensional chip with f More
Three-Dimensional Chips are made of stacking silicon layers which communicate with each other by Through-Silicon-Via (TSV) links. Manufacturing cost of Three-Dimensional chips is a function of the number of TSVs because the fabricating of a three-dimensional chip with fully vertical links is of high cost and high fabrication complexity.
The packet routing strategies in the 3D NoCs with partially TSVs is more complex than that in the 2D NoCs. In this paper, we proposed a routing algorithm for the 3D NoCs with partial TSVs, which provides a dynamic routing with maximum adaptivity for packets by dividing the network into three groups of layers, rows and columns. This algorithm is independent of vertical channel's position but related to layer number of the current packet and based on the layer number, odd or even, uses a special turn strategy to route packets on rows and columns with odd or even numbers. The proposed routing algorithm mitigates deadlock and livelock with only two virtual. The experiments show that average packet latency in proposed algorithm is 32.8% smaller than that in Elevator_First which is a well-known algorithm for packet routing in 3D chips. Also, this improvement on average packet latency and network throughput will be more with increasing on network size and reduction on TSV number.
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