Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method
Subject Areas : electrical and computer engineering
امیرمحمد
حاجی صادقی
1
حمیدرضا
زرندی
2
(Amirkabir Univ of Tech)
Sh.
Jalilian
3
Keywords: Emerging non-volatile memory, STT-MRAM memory, write energy, process variation (PV), write error (WE),
Abstract :
With the advancement of technology and the shrinking dimensions of transistors in CMOS technology, several challenges have arisen. One of the main concerns in using CMOS-based memory is the high power consumption of this type of memory. Therefore, new and non-volatile memories were introduced to address the shortcomings of conventional volatile memory. One of the emerging non-volatile technologies is STT-MRAM memory, an effective and efficient alternative to conventional memory such as SRAMs due to low leakage power, high density, and short access time. The positive features of STT-MRAMs make it possible to use them at different memory hierarchy levels, especially the cache level. However, STT-MRAMs suffer from high write energy. In this paper, we present a new write circuit using the temperature method; in addition to improving the high write energy, write delay is also improved. The proposed circuit lead to 22.5% and 18.62% improvement in energy and writing delay, respectively, compared to the existing methods.
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