ارائه مدار نوشتن جدید جهت کاهش انرژی و تأخیر عملیات نوشتن در حافظه‌های STT-MRAM با بهره‌گیری از روش دمایی
محورهای موضوعی : مهندسی برق و کامپیوتر
امیرمحمد حاجی صادقی
1
(دانشگاه صنعتی امیرکبیر)
حمیدرضا زرندی
2
(دانشگاه صنعتی امیرکبیر)
شاهرخ جلیلیان
3
(پژوهشگاه فضایی ایران)
کلید واژه: حافظه غیر فرار نوظهور, حافظه STT-MRAM, انرژی عملیات نوشتن, نوسانات فرایند ساخت, خطای نوشتن,
چکیده مقاله :
با پیشرفت تکنولوژی و کوچک‌ترشدن ابعاد ترانزیستورها در تکنولوژی CMOS، چالش‌های متعددی به وجود آمده‌اند. از نگرانی‌های اصلی در بهره‌گیری از حافظه‌های مبتنی بر CMOS، می‌توان توان مصرفی بالا در این نوع حافظه‌ها را برشمرد. از این رو برای مرتفع‌نمودن کمبودهای حافظه‌های فرار مرسوم، حافظه‌های جدید و غیر فراری ارائه شدند. در این میان یکی از تکنولوژی‌های غیر فرار نوظهور، حافظه‌های STT-MRAM هستند که به واسطه ویژگی‌هایی همچون توان نشتی ناچیز، چگالی بالا و زمان دسترسی مناسب به عنوان جایگزینی مؤثر و کارا برای حافظه‌های مرسوم همچون SRAMها در نظر گرفته می‌شوند. ویژگی‌های مثبت STT-MRAMها این امکان را به وجود می‌آورد که بتوان از آنها در سطوح مختلف از سلسله‌مراتب حافظه، علی‌الخصوص سطح حافظه نهان بهره برد. با این حال، حافظه‌های STT-MRAM از انرژی نوشتن بالا رنج می‌برند که در این مقاله با ارائه یک مدار نوشتن جدید با بهره‌گیری از روش دمایی، علاوه بر بهبود انرژی بالای نوشتن در این نوع حافظه، تأخیر نوشتن نیز بهبود داده می‌شود. روش پیشنهادی در مقایسه با روش‌های موجود به بهبودی 5/22 و 62/18 درصدی به ترتیب در انرژی و تأخیر نوشتن دست یافته است.
With the advancement of technology and the shrinking dimensions of transistors in CMOS technology, several challenges have arisen. One of the main concerns in using CMOS-based memory is the high power consumption of this type of memory. Therefore, new and non-volatile memories were introduced to address the shortcomings of conventional volatile memory. One of the emerging non-volatile technologies is STT-MRAM memory, an effective and efficient alternative to conventional memory such as SRAMs due to low leakage power, high density, and short access time. The positive features of STT-MRAMs make it possible to use them at different memory hierarchy levels, especially the cache level. However, STT-MRAMs suffer from high write energy. In this paper, we present a new write circuit using the temperature method; in addition to improving the high write energy, write delay is also improved. The proposed circuit lead to 22.5% and 18.62% improvement in energy and writing delay, respectively, compared to the existing methods.
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