%0 Journal Article %T Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method %J Nashriyyah -i Muhandisi -i Barq va Muhandisi -i Kampyutar -i Iran %I Iranian Research Institute for Electrical Engineering %Z 16823745 %A Amir M Hajisadeghi %A Hamid Reza Zarandi %A Sh. Jalilian %D 1400 %\ 1400/07/12 %V 1 %N 19 %P 27-34 %! Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method %K Emerging non-volatile memory %K STT-MRAM memory %K write energy %K process variation (PV) %K write error (WE) %X With the advancement of technology and the shrinking dimensions of transistors in CMOS technology, several challenges have arisen. One of the main concerns in using CMOS-based memory is the high power consumption of this type of memory. Therefore, new and non-volatile memories were introduced to address the shortcomings of conventional volatile memory. One of the emerging non-volatile technologies is STT-MRAM memory, an effective and efficient alternative to conventional memory such as SRAMs due to low leakage power, high density, and short access time. The positive features of STT-MRAMs make it possible to use them at different memory hierarchy levels, especially the cache level. However, STT-MRAMs suffer from high write energy. In this paper, we present a new write circuit using the temperature method; in addition to improving the high write energy, write delay is also improved. The proposed circuit lead to 22.5% and 18.62% improvement in energy and writing delay, respectively, compared to the existing methods. %U http://rimag.ir/fa/Article/28911