تولید الگوی آزمون خودکار پیشرفته با استفاده از الگوریتم PSO-FAN
محورهای موضوعی : مهندسی برق و کامپیوتر
سید حمید ظهیری
1
*
,
احسان حق پرست
2
,
ابوالفضل بیجاری
3
1 - دانشكده مهندسي برق و كامپيوتر، دانشگاه بیرجند، بیرجند، ایران
2 - دانشکده مهندسی برق و کامپیوتر, دانشگاه بیرجند, بیرجند, ایران
3 - دانشكده مهندسي برق و كامپيوتر، دانشگاه بیرجند، بیرجند، ایران
کلید واژه: تولید خودکار الگوی آزمون, بهینه سازی, مدارات VLSI, الگوریتم های فراابتکاری, الگوریتم FAN,
چکیده مقاله :
حوزه آزمایش مدارهای یکپارچه با مقیاس بسیار بزرگ (VLSI) در سالهای اخیر پیشرفتهای قابل توجهی در روشهای تشخیص خطا تجربه کرده است، به طوری که این پیشرفتها در کاربردهای پیچیده اهمیت فراوانی یافتهاند. هرچند که روشهای سنتی برای شناسایی مدارهای سالم و معیوب کارآمد هستند، اما معمولاً در تشخیص دقیق انواع مختلف خطا محدودیتهایی دارند. این مقاله به بررسی پیادهسازی یک الگوریتم بهینهسازی شده به نام FAN (الگوریتم تولید تست مبتنی بر خروجی) میپردازد که با استفاده از تکنیک بهینهسازی ازدحام ذرات (PSO) بر روی مدارهای معیاری ISCAS'89 انجام شده است. نتایج حاصل از این مطالعه نشاندهنده بهبود در پوشش خطا و افزایش دقت تشخیص میباشد. به علاوه، این بهینهسازی منجر به کاهش تعداد بردارهای آزمایشی مورد نیاز گردیده است که در نتیجه کارایی آزمایش را در شرایط تولید با حجم بالا افزایش میدهد. این تحقیق بر اهمیت توسعه معیارهای تشخیصی به منظور درک بهتر عیوب مدار تأکید میکند و بهکارگیری تکنیکهای طراحی که قابلیت آزمایش را تقویت کند، پیشنهاد مینماید. استفاده از PSO در الگوریتم FAN، نشاندهنده پتانسیل بالای این روش در فرآیند تولید تست است و موجب برقراری تعادلی مناسب بین دقت، پیچیدگی و کارایی عملیاتی میشود.
The domain of Very Large Scale Integrated (VLSI) circuit testing has experienced advancements in methodologies for fault detection, which are crucial for addressing the complexities of modern applications. Traditional testing techniques frequently fall short in achieving precise fault localization, highlighting the necessity for the development of enhanced methodologies. This paper endeavors to investigate the implementation of an optimized test generation algorithm aimed at improving testing efficiency and increasing fault coverage. In this study, we utilized a (PSO)-enhanced FAN (fan-out-oriented algorithm) applied to ISCAS'89 benchmark circuits. The optimization process involved refining the decision trees utilized in the FAN algorithm through a rigorously defined cost function, which strikes a balance between accuracy, complexity, and operational efficiency. The results indicate improvement in both fault coverage and detection efficiency. Furthermore, the optimization process resulted in a reduction of required test vectors, thereby enhancing testing efficiency, particularly in high-volume production environments. The study also introduces the development of diagnostic metrics that provide deeper insights into circuit failures and proposes design-for-testability techniques to improve reliability. The integration of PSO within the FAN algorithm not only facilitates the generation of robust test solutions but also produces high-quality test vectors.
[1] Lai, Y., Liu, J., Tang, Z., Wang, B., Hao, J., & Luo, P. (2023, July). Chipformer: Transferable chip placement via offline decision transformer. In International Conference on Machine Learning (pp. 18346-18364). PMLR.
[2] Gaber L, Hussein AI, Moness M (2019) Improved automatic correction for digital VLSI circuits. In 2019 Proceeding 31st international conference on microelectronics (ICM), 2019, pp 18–22.
[3] Shanthi, J., Rani, D. G. N., & Rajaram, S. (2022). A C4. 5 decision tree classifier based floorplanning algorithm for System-on-Chip design. Microelectronics journal, 121, 105361.
[4] Alateeq, M., & Pedrycz, W. (2021). A comparative analysis of bio-inspired optimization algorithms for automated test pattern generation in sequential circuits. Applied Soft Computing, 101, 106967.
[5] Lee, S. H., Lee, S. J., Park, J., Lee, E. C., & Kang, H. G. (2018). Development of simulation-based testing environment for safety-critical software. Nuclear Engineering and Technology, 50(4), 570-581.
[6] Gaudesi, M., Pomeranz, I., Reorda, M. S., & Squillero, G. (2016). New techniques to reduce the execution time of functional test programs. IEEE Transactions on Computers, 66(7), 1268-1273.
[7] Letia, T. S., & Kilyen, A. O. (2016, May). Fuzzy logic enhanced time Petri Net models for hybrid control systems. In 2016 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) (pp. 1-6). IEEE.
[8] Gaudesi, M., Pomeranz, I., Reorda, M. S., & Squillero, G. (2016). New techniques to reduce the execution time of functional test programs. IEEE Transactions on Computers, 66(7), 1268-1273.
[9] Gaudesi, M., Reorda, M. S., & Pomeranz, I. (2015, May). On test program compaction. In 2015 20th IEEE European Test Symposium (ETS) (pp. 1-6). IEEE.
[10] Eggersglüß, S., Milewski, S., Rajski, J., & Tyszer, J. (2021, October). On reduction of deterministic test pattern sets. In 2021 IEEE International Test Conference (ITC) (pp. 260-267). IEEE.
[11] Gaudesi, M., Reorda, M. S., & Pomeranz, I. (2015, May). On test program compaction. In 2015 20th IEEE European Test Symposium (ETS) (pp. 1-6). IEEE.
[12] Wang, P., Moore, C. J., Gharehbaghi, A. M., & Fujita, M. (2017). An ATPG method for double stuck-at faults by analyzing propagation paths of single faults. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(3), 1063-1074.
[13] Malihi, L., & Malihi, R. (2020). Single stuck-at-faults detection using test generation vector and deep stacked-sparse-autoencoder. SN Applied Sciences, 2(10), 1715.
[14] Shah, T., Matrosova, A., Fujita, M., & Singh, V. (2018). Multiple stuck-at fault testability analysis of ROBDD based combinational circuit design. Journal of Electronic Testing, 34, 53-65.
[15] Singh, V. K., Sarkar, T., & Pradhan, S. N. (2022). Power-aware testing for maximum fault coverage in analog and digital circuits simultaneously. IETE Technical Review, 39(6), 1395-1409.
[16] Gaber, L., Hussein, A. I., & Moness, M. (2021). Fault detection based on deep learning for digital VLSI circuits. Procedia Computer Science, 194, 122-131.
[17] Hu, H., Feng, F., & Wang, T. (2020). Open-circuit fault diagnosis of NPC inverter IGBT based on independent component analysis and neural network. Energy Reports , 6 , 134-143.
[18] Wang T, Xu H, Han J et al (2015) Cascaded H-bridge multilevel inverter system fault diagnosis using a PCA and multi-class relevance vector machine approach. IEEE Trans Power Electr 30(12):1.
[19] Yin, Z., Wang, L., Zhang, Y., & Gao, Y. (2019). A novel arc fault detection method integrated random forest, improved multi-scale permutation entropy and wavelet packet transform. Electronics, 8(4), 396.
[20] Simonyan K, Zisserman A (2015) Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv :1409.1556.
[21] Wu, Z., Pan, S., Chen, F., Long, G., Zhang, C., & Philip, S. Y. (2020). A comprehensive survey on graph neural networks. IEEE transactions on neural networks and learning systems, 32(1), 4-24.
[22] Wu, H., & Zhao, J. (2018). Deep convolutional neural network model based chemical process fault diagnosis. Computers & chemical engineering, 115, 185-197.
[23] Zhang Z, Zhao J (2017) A deep belief networkbased fault diagnosis model for complex chemical processes. Comput Chem Eng 107:395–407.
[24] Liu, W., Wang, Z., Liu, X., Zeng, N., Liu, Y., & Alsaadi, F. E. (2017). A survey of deep neural network architectures and their applications. Neurocomputing, 234, 11-26.
[25] Wang, H., Fu, T., Du, Y., Gao, W., Huang, K., Liu, Z., ... & Zitnik, M. (2023). Scientific discovery in the age of artificial intelligence. Nature, 620(7972), 47-60.
[26] Sarker, I. H. (2021). Machine learning: Algorithms, real-world applications and research directions. SN computer science, 2(3), 160.
[27] Xie Y, Zeng H, Hu C, Ji Z (2019) Security/timming-aware design space exploration of CAN FD for automative cyber-phsical systems. IEEE Trans Ind Inf 15(2):1094–1104.
[28] Xiao H, Cao M, Peng R (2020) Artificial neural networkbased software fault detection and correction prediction models considering testing effort. Appl Soft Comput 94:106491.
[29] Jiang W, Wen L, Zhan J, Jiang K (2020) Design optimization of confidentiality-critical cyber physical systems with fault detection. J Syst Archit 107:101739.
[30] Md Younus Ali, Raimund Ubar, (2020) TESTIDE GENEREERIMINE VIIVITUSRIKETELE DIGITAALSKEEMIDES, Tallinn University of Technology.
[31] Miller, D. M., & Thornton, M. A. (2022). Multiple-Valued Logic: Concepts and Representations. Springer Nature.
[32] Dorf, R. C. (2018). The Electrical Engineering Handbook-Six Volume Set. CRC press.
[33] Fujiwara H (1985) Fan: a fanout-oriented test pattern generation algorithm. In: Proceedings of IEEE international symposium circuits system, pp 671–674.
[34] Khan, S., & Sarkar, P. (2023, December). A Comprehensive Review of Machine Learning Applications in VLSI Testing: Unveiling the Future of Semiconductor Manufacturing. In 2023 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) (pp. 1-5). IEEE.