Enhanced Automatic Test Pattern Generation Using PSO-FAN Algorithm
Subject Areas : مهندسی برق و کامپیوتر
S. H. Zahiri
1
*
,
Ehsan Haghparast
2
,
Abolfazl Bijari
3
1 - University of Birjand
2 - Department of Electronics Engineering, University of Birjand, Birjand, Iran
3 - Department of Electronics Engineering, University of Birjand, Birjand, Iran
Keywords: Fault Detection, ATPG, Optimization, VLSI Circuits, Heuristic Algorithms, FAN Algorithm,
Abstract :
The domain of Very Large Scale Integrated (VLSI) circuit testing has experienced advancements in methodologies for fault detection, which are crucial for addressing the complexities of modern applications. Traditional testing techniques frequently fall short in achieving precise fault localization, highlighting the necessity for the development of enhanced methodologies. This paper endeavors to investigate the implementation of an optimized test generation algorithm aimed at improving testing efficiency and increasing fault coverage. In this study, we utilized a (PSO)-enhanced FAN (fan-out-oriented algorithm) applied to ISCAS'89 benchmark circuits. The optimization process involved refining the decision trees utilized in the FAN algorithm through a rigorously defined cost function, which strikes a balance between accuracy, complexity, and operational efficiency. The results indicate improvement in both fault coverage and detection efficiency. Furthermore, the optimization process resulted in a reduction of required test vectors, thereby enhancing testing efficiency, particularly in high-volume production environments. The study also introduces the development of diagnostic metrics that provide deeper insights into circuit failures and proposes design-for-testability techniques to improve reliability. The integration of PSO within the FAN algorithm not only facilitates the generation of robust test solutions but also produces high-quality test vectors.
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