Modeling a Proposed Nanoscale SOI-Junctionless for Improvement of Steady-State and Frequency Characteristics
Subject Areas : electrical and computer engineering
Mohammad Kazem
Anvarifard
1
(فني و مهندسي شرق گيلان)
Keywords: Buried oxide, junctionless, silicon-on-insulator, buffer layer,
Abstract :
In this paper in order to improve the electrical performance of nanoscale SOI-junctionless, a targeted modification has been performed. The proposed structure has been aimed to reduce the OFF current and self-heating effect. To reduce the self-heating effect, the buried oxide thickness has been reduced into the half and a part of it has been replaced by a buffer layer. Increase in the thermal conduction and making an extra depletion layer in the buffer layer/channel region interface are led to improvement of the electrical performance in the terms of DC and AC. In the proposed method, which is based on the energy band modification, the parameters such as IOFF, ION/IOFF, subthreshold swing, lattice temperature, voltage gain, transconductance, parasitic capacitances, power gains, cut-off frequency, maximum oscillation frequency and minimum noise figure have been improved. Also, a designing consideration for the role of buffer layer on the proposed device has been performed. Comparing structures under the study simulated by the SILVACO showed the electrical performance superiority for the proposed device.
[1] M. K. Anvarifard and A. A. Orouji, "Voltage difference engineering in SOI MOSFETs: a novel side gate device with improved electrical performance," Materials Science in Semiconductor Processing, vol. 6, no. 1, pp. 1672-1678, Dec. 2013.
[2] M. Rahimian, A. A. Orouji, and A. H. Aminbeidokhti, "A novel deep submicron SiGe-on-insulator (SGOI) MOSFET with modified channel band energy for electrical performance improvement," Current Applied Physics, vol. 13, no. 4, pp. 779-784, Jun. 2013.
[3] M. Mehrad, "Controlling floating body effect in high temperatures: L-shape SiGe region in nano-scale MOSFET," Superlattices and Microstructures, vol. 85pp. 573-580, Sep. 2015.
[4] A. A. Orouji and M. Jagadesh Kumar, "A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain," Microelectronic Engineering, vol. 83, no. 3, pp. 409-414, Mar. 2006.
[5] س. کلانتری و م. وادی‌زاده، "کاهش جریان خاموشی در ترانزیستور اثر میدان بدون پیوند دوگیتی نانومتری با استفاده از مهندسی آلایش میانه کانال،" نشریه مهندسی برق و مهندسی کامپیوتر ایران، الف- مهندسی برق، جلد 16، شماره 1، صص. 42-37، بهار 1397.
[6] م. وادی‌زاده، س. ص. قریشی و م. فلاح‌نژاد، "استفاده از گیت کمکی برای بهبود مشخصات الکتریکی ترانزیستور اثر میدان بدون پیوند سیلیکون بر روی عایق،" نشریه مهندسی برق و مهندسی کامپیوتر ایران، الف- مهندسی برق، جلد 18، شماره 1، صص. 72-67، بهار 1399.
[7] س. م. رضوی، س. ح. ظهیری و س. ا. حسینی، "بررسی مشخصه‌های الکتریکی AlGaN/GaN-HEMT با واردکردن لایه P در لایه سد در دو سمت سورس و درین،" نشریه مهندسی برق و مهندسی کامپیوتر ایران، الف- مهندسی برق، جلد 15، شماره 3، صص. 222-217، پاییز 1396.
[8] Z. Ramezani and A. A. Orouji, "Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET," Superlattices and Microstructures, vol. 98, pp. 359-370, Oct. 2016.
[9] M. Rahimian and A. A. Orouji, "Investigation of the electrical and thermal performance of SOI MOSFETs with modified channel engineering," Materials Science in Semiconductor Processing, vol. 16, no. 5, pp. 1248-1256, Oct. 2013.
[10] J. P. Colinge, et al., "Junctionless nanowire transistor (JNT): properties and design guidelines," Solid-State Electronics, vol. 65/66, pp. 33-37, Nov./Dec. 2011.
[11] R. K. Baruah and R. P. Paily, "A dual-material gate junctionless transistor with high-k spacer for enhanced analog performance," IEEE Trans. on Electron Devices, vol. 61, no. 1, pp. 123-128, Jan. 2014.
[12] X. Jin, M. Wu, X. Liu, R. Chuai, H. I. Kwon, J. H. Lee, and J. H. Lee, "A novel high performance junctionless FETs with saddle-gate," J. of Computational Electronics, vol. 14, no. 3, pp. 661-668, May 2015.
[13] C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti Akhavan, P. Razavi, and J. P. Colinge, "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol. 54, no. 2, pp. 97-103, Feb. 2010.
[14] Y. Song, et al., "III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications," IEEE Electron Device Letters, vol. 35, no. 3, pp. 324-326, Mar. 2014.
[15] S. Min Lee, H. Jun Jang, and J. T. Park, "Impact of back gate biases on hot carrier effects in multiple gate junctionless transistors," Microelectronics Reliability, vol. 53, no. 9-11, pp. 1329-1332, Nov. 2013.
[16] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nature Nanotechnology, vol. 5, no. 3, pp. 225-229, Mar. 2010.
[17] S. Gundapaneni, S. Ganguly, and A. Kottantharayil, "Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling," IEEE Electron Device Letters, vol. 32, no. 3, pp. 261-263, Mar. 2011.
[18] R. Yan, A. Kranti, I. Ferain, C. W. Lee, R. Yu, N. Dehdashti, P. Razavi, and J. P. Colinge, "Investigation of high-performance sub-50 nm junctionless nanowire transistors," Microelectronics Reliability, vol. 51, no. 7, pp. 1166-1171, Jul. 2011.
[19] M. Rahimian and M. Fathipour, "Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric," Materials Science in Semiconductor Processing, vol. 63, pp. 142-152, Jun. 2017.
[20] M. Rahimian and M. Fathipour, "Junctionless nanowire TFET with built-in N-P-N bipolar action: physics and operational principle," J. of Applied Physics, vol. 120, Article No.: 225702, 2016.
[21] SILVACO International, ATLAS User's Manual: 2-D Device Simulator, Santa Clara, CA, USA, 2016.
[22] W. B. Joyce and R. W. Dixon, "Analytic approximation for the fermi energy of an ideal fermi gas," Appl. Phys Lettvol. 31, no. 5, pp. 354-356, 1978.
[23] S. Selberherr, Analysis and Simulation of Semiconductor Devices, Wien, New York: Springer-Verlag, 1984.
[24] Z. Yu and R. W. Dutton, SEDAN III-A Generalized Electronic Material Device Analysis Program, Stanford Electronics Laboratory Technical Report, Stanford University, Jul. 1985.
[25] M. K. Anvarifard and A. A. Orouji, "Evidence for enhanced reliability in a novel nanoscale partially-depleted SOI MOSFET," IEEE Trans. on Device and Materials Reliability, vol. 15, no. 4, pp. 536-542, Dec. 2015.