Observable Optimized Selective Hardening of Combinational Circuits against Soft-Error
Subject Areas : electrical and computer engineeringKeywords: Soft error combinational circuit observability reliability critical charge,
Abstract :
Due to the shrinking of feature size, reduction in supply voltage and technology scaling, the sensitivity to radiation induced transient faults of digital systems has dramatically increased. Soft error causes transient distortion in circuit operation and is expected to become very important in combinational logic with increment of the circuit frequency. In this paper, we introduce an optimized method for hardening of combinational logic circuits against soft errors. In this method, first we have found the most sensitive nodes of the circuit by observability computations. Next for optimizing power-delay product and area, the reliability of the circuit has been computed and the number of the necessary nodes for hardening will be identified. In the next step, three different hardening methods including time redundancy, Schmitt trigger and transistor feedback have been carried out on standard test circuits as our vehicles. The comparison of three method results show that the hardened circuits with Schmitt trigger have the most cumulative critical charge and the least power-delay product and lead to an optimum hardening. Moreover, the simulation results approve the optimized hardening is obtained from suitable selecting the number of required nodes considering observability concepts and reliability computations together with the best node hardening method. Monte-Carlo simulations also approve the performance of the proposed method against process variations.
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