ارائه تمام‌جمع‌کننده‌های تقریبی با خطای کم و آگاه از تغییرپذیری برای کاربردهای تحمل پذیر عدم دقت
محورهای موضوعی : مهندسی برق و کامپیوترمحمد میرزایی 1 , سيامك محمدي 2 *
1 - دانشگاه تهران،دانشکده مهندسی برق و کامپیوتر
2 - دانشگاه تهران،دانشکده مهندسی برق و کامپیوتر
کلید واژه: تغییرپذیری, تمام‌جمع‌کننده تقریبی, جمع‌کننده تقریبی, کاربردهای تحمل‌پذیر عدم دقت, محاسبات تقریبی,
چکیده مقاله :
کاربردهای تحمل‌پذیر عدم دقت مانند پردازش تصویر و یادگیری ماشین به دلیل محدودیت‌های حس انسان یا ماهیت کاربرد، قابلیت تحمل عدم دقت را دارند. استفاده از محاسبات تقریبی در این کاربردها می‌تواند به کاهش قابل توجهی در توان، تأخیر و مساحت منجر شود. در این مقاله دو تمام‌جمع‌کننده تقریبی و یک جمع‌کننده تقریبی با خطای کم ارائه شده و اثرات تغییرپذیری قالب به قالب ولتاژ آستانه روی این مدارها مورد ارزیابی قرار گرفته است. برای ارزیابی خطا و تغییرپذیری، از این تمام‌جمع‌کننده‌های تقریبی در ساختار جمع‌کننده با انتشار نقلی و الگوریتم‌های پردازش تصویر sharpening و smoothing استفاده شده است. از نظر سه پارامتر حاصل‌ضرب- توان- تأخیر، دقت و مساحت برای ورودی‌های با توزیع یکنواخت، تمام‌جمع‌کننده پیشنهادی 1 و از نظر حداکثر نسبت سیگنال به نویز برای کاربردهای واقعی، تمام‌جمع‌کننده پیشنهادی 2 و جمع‌کننده پیشنهادی، بهترین عملکرد را دارند.
In imprecision-tolerant applications such as image processing and machine learning, imprecision can be tolerated because of the nature of the application itself or the limitation of human senses. By using the approximate computation in these applications, significant power, delay, or area reductions can be achieved. In this paper, two approximate full adders and an approximate adder, with low error are proposed. The effects of die-to-die (D2D) process variation on the threshold voltage of approximate circuits have been evaluated. For evaluating the accuracy and the variability, these approximate full adders have been used and analyzed in the ripple carry adder structure, image Sharpening and image Smoothing algorithms. In terms of power-delay-product (PDP), accuracy, and area for uniformly distributed inputs, the proposed approximate full adder 1, exhibits the best performance, and the proposed approximate full adder 2 and the proposed approximate adder, show the best peak-signal-to-noise ratio (PSNR) for real images.
[1] M. A. Laurenzano, P. Hill, M. Samadi, S. Mahlke, J. Mars, and L. Tang, "Input responsiveness: using canary inputs to dynamically steer approximation," ACM SIGPLAN Notices, vol. 51, no. 6, pp. 161-176, Santa Barbara CA, USA, 13 - 17 Jun. 2016.
[2] H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, "Architecture support for disciplined approximate programming," ACM SIGPLAN Notices, vol. 47, no. 4, pp. 301-312, London UK, 3-7 Mar. 2012.
[3] S. Mittal, "A survey of techniques for approximate computing," ACM Computing Surveys, vol. 48, no. 4, Article ID: 62, 33 pp., May 2016.
[4] H. Jiang, C. Liu, L. Liu, F. Lombardi, and J. Han, "A review, classification, and comparative evaluation of approximate arithmetic circuits," ACM J. on Emerging Technologies in Computing Systems, vol. 13, no. 4, Article ID: 60, pp 1-34, Oct. 2017.
[5] C. Hernandez, A. Roca, F. Silla, J. Flich, and J. Duato, "On the impact of within-die process variation in GALS-based NoC performance," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 294-307, Feb. 2012.
[6] M. Mirzaei, M. Mosaffa, and S. Mohammadi, "Variation-aware approaches with power improvement in digital circuits," Integration, the VLSI J., vol. 48, pp. 83-100, Jan. 2015.
[7] M. Mirzaei, M. Mosaffa, S. Mohammadi, and J. Trajkovic, "Power and variability improvement of an asynchronous router using stacking and dual-Vth approaches," in Proc. Euromicro Conf. on Digital System Design, pp. 327-334, Los Alamitos, CA, USA, 4-6 Sert. 2013.
[8] S. M. T. Adl, M. Mirzaei, and S. Mohammadi, "Elastic buffer evaluation for link pipelining under process variation," IET Circuits, Devices & Systems, vol. 12, no. 5, pp. 645-654, Sept. 2018.
[9] M. Mirzaei and S. Mohammadi, "Low-power and variation-aware approximate arithmetic units for Image Processing Applications," AEU-International J. of Electronics and Communications, vol. 138, Article ID: 153825, 13 pp., Aug. 2021.
[10] M. Mirzaei and S. Mohammadi, "Process variation-aware approximate full adders for imprecision-tolerant applications," Computers & Electrical Engineering, vol. 87, Article ID: 106761, 14 pp., Oct. 2020.
[11] T. Yang, T. Ukezono, and T. Sato, "A low-power configurable adder for approximate applications," in Proc. 19th Int. Symp. on Quality Electronic Design, ISQED’18, pp. 347-352, Santa Clara, CA, USA, 13-14 Mar. 2018.
[12] T. Ukezono, "An error corrector for dynamically accuracy-configurable approximate adder," in Proc. 6th Int. Symp. on Computing and Networking Workshops, CANDARW’18, pp. 145-151, Takayama, Japan, 27-30 Nov. 2018.
[13] H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, "Bio-inspired imprecise computational blocksfor efficient VLSI implementation of soft-computing applications," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 57, no. 4, pp. 850-862, Apr. 2009.
[14] A. M. Hassani, M. Rezaalipour, and M. Dehyadegari, "A novel ultra low power accuracy configurable adder at transistor level in Proc. 8th Int.Conf. on Computer and Knowledge Engineering, ICCKE’18, pp. 165-170, Mashhad, Iran, 25-26 Oct. 018.
[15] A. Dalloo, A. Najafi, and A. Garcia-Ortiz, "Systematic design of an approximate adder: the optimized lower part constant-or adder," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1595-1599, Aug. 2018.
[16] L. B. Soares, M. M. A. da Rosa, C. M. Diniz, E. A. C. da Costa, and S. Bampi, "Design methodology to explore hybrid approximate adders for energy-efficient image and video processing accelerators," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 66, no. 6, pp. 2137-2150, Jun. 2019.
[17] S. Mazahir, M. K. Ayub, O. Hasan, and M. Shafique, "Probabilistic error analysis of approximate adders and multipliers," Approximate Circuits: Springerpp. 99-120, Dec. 2019.
[18] Y. Wu, Y. Li, X. Ge, Y. Gao, and W. Qian, "An efficient method for calculating the error statistics of block-based approximate adders," IEEE Trans. on Computers, vol. 68, no. 1, pp. 21-38, Jan. 2018.
[19] O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, "RAP-CLA: a reconfigurable approximate carry look-ahead adder," IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 65, no. 8, pp. 1089-1093, Nov. 2016.
[20] H. A. Almurib, T. N. Kumar, and F. Lombardi, "Approximate DCT image compression using inexact computing," IEEE Trans. on Computers, vol. 67, no. 2, pp. 149-159, Jul. 2017.
[21] V. Gupta, D. Mohapatra, S. P. Park, A. Raghunathan, and K. Roy, "IMPACT: imprecise adders for low-power approximate computing," in Proc. of the 17th IEEE/ACM Int. Symp. on Low-Power Electronics and Design, pp. 409-414, Fukuoka, Japan, 1-3 Aug. 2011.
[22] V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, "Low-power digital signal processing using approximate adders," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 124-137, Dec. 2012.
[23] Z. Yang, A. Jain, J. Liang, J. Han, and F. Lombardi, "Approximate XOR/XNOR-based adders for inexact computing," in Proc. 13th IEEE Int. Conf. on Nanotechnology, IEEE-NANO’13, pp. 690-693, Beijing, China, 5-8 Aug. 2013.
[24] H. A. Almurib, T. N. Kumar, and F. Lombardi, "Inexact designs for approximate low power addition bycell replacement," in Proc. Design, Automation & Test in Europe Conf. & Exhibition, DATE’16, , pp. 660-665, Dresden, Germany, 14-18 Mar. 2016.
[25] N. H. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Pearson Education India, 2015.
[26] Z. Yang, J. Han, and F. Lombardi, "Transmission gate-based approximate adders for inexact computing," in Proc. of the IEEE/ACM Int. Symp. on Nanoscale Architectures, NANOARCH'15, pp. 145-150, Boston, MA, USA, 08-10 Jul. 2015.
[27] S. Venkatachalam and S. B. Ko, "Design of power and area efficient approximate multipliers," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 5, pp. 1782-1786, Jan. 2017.
[28] H. Waris, C. Wang, and W. Liu, "High-performance approximate half and full adder cellsusing NAND logic gate," IEICE Electronics Express, vol.16, no.6, pp. 36-43, Jun. 2019.
[29] Y. S. Mehrabani, S. G. Gigasari, M. Mirzaei, and H. Uoosefian, "A novel highly-efficient inexact full adder cell for motion and edge detection systems of image processing in CNFET technology," ACM J. of Emerging Technologies in Computing System, vol. 18, no. 3, pp. 127-142, Mar. 2022.
[30] Z. Zareei, M. Bagherizadeh, M. Shafiabadi, and Y. S. Mehrabani, "Design of efficient approximate 1-bit full adder cells using CNFET technology applicable in motion detector systems," Microelectronics J., vol. 108, Article ID: 104962, 15 pp., Feb. 2021.
[31] S. H. Shahrokhi, M. Hosseinzadeh, M. Reshadi, and S. Gorgin, "High-performance and low-energy approximate full adder design for error-resilient image processing," International J. of Electronics, vol. 109, no. 6, pp. 1059-1079, Aug. 2021.
[32] Y. S. Mehrabani, M. Parsapour, M. Moradi, and M. Bagherizadeh, "A novel efficient CNFET-based inexact full adder design for image processing applications," International J. of Nanoscience, vol. 20, no. 2, pp. 21-30, Jan. 2015.
[33] S. Salavati, M. H. Moaiyeri, and K. Jafari, "Ultra-efficient nonvolatile approximate full-adder with spin-Hall-assisted MTJ cells for in-memory computing applications," IEEE Trans. on Magnetics, vol. 57, no. 5, pp. 1-11, Mar. 2021.
[34] G. Gulafshan, D. Hasan, and M. Khan, "Fast and Area Efficient Hybrid MTJ-CMOS Spintronic Approximate Adder," in Proc. , 5th IEEE Int. Conf. on Emerging Electronic, ICEE’20, New Delhi, India, 26-28 Nov. 2022.
[35] -, Predictive Technology Model, Retrived on Jan. 2, 2020, http://ptm.asu.edu
[36] H. R. Myler and A. R. Weeks, The Pocket Handbook of Image Processing Algorithms in C, Prentice Hall Press, 2009.
[37] Z. Wang, A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli, "Image quality assessment: from error visibility to structural similarity," IEEE Trans. on Image Processing, vol. 13, no. 4, pp. 600-612, Apr. 2004.