Analysis of SettlingTime in Charge Pump Phase-Locked loops regarding Non-ideal Effect
Subject Areas : electrical and computer engineeringhadi dehbovid 1 * , habib Adarang 2 , hamidreza rabiee 3
1 - Departmet of Electrical Engineering, Nour Branch, Islamic Azad University, Nour, Iran
2 - Department of Electrical Engineering, nour branch, Islamic azad university, nour, iran
3 - Department of Electrical Engineering, karaj branch, Islamic azad university, karaj, iran
Keywords: Phase-locked loop (PLL), charge pump current, phase detector, channel length modulation effect, settling time,
Abstract :
Phase locked loops (PLL) are widely used in telecommunication systems. Frequency characteristics and settling time are the two most important features of PLLs. In phase lock loops, several nonlinear factors can be considered, one of which is the nonlinear behavior of the phase detector. In fact, load pump phase locking loops (CPPLL) are nonlinear systems due to the nonlinear behavior generated by the load pump. Although the applied current is fixed in an ideal load pump, this is not fixed in practice because of the non-ideal behavior of the transistors. In this paper, considering the channel length modulation (CLM) effect caused by the drain-source voltage of MOSFET transistor, a more accurate model is presented for the phase detector. By investigating the non-linear differential equation dominating the system and using the step-response approximation for the transient time analysis, new equations are obtained for the settling time and overshooting. In order to check the validity of the specified non-linear equations, the simulation was conducted in MATLAB Simulink. Moreover, in order to better assess the proposed method, the performance of a PLL subjected to the transistor’s drain-source voltage has been simulated and the effect of the different loop parameters, such as the loop’s resistor and current has been investigated. The final results showed the appropriate accordance of the analytical equations with the simulation results.
[1] K. Woo, Y. Liu, E. Nam, and D. Ham, "Fast-lock hybrid PLL combining fractional-N and integer modes of differing bandwidths," IEEE J. of Solid-State Circuits, vol. 43, no. 2, pp. 379-389, Feb. 2008.
[2] M. H. Perrot, Analogue Frequency Synthesizers, Short Course on Phase-Locked Loops, IEEE Circuits and Systems Society, San Diego, CA, USA, 2009.
[3] P. K. Hanumolu, M. Brownlee, K. Mayaram, and U. K. Moon, "Analysis of charge-pump phase-lock loops," IEEE Trans. on Circuits and Systems, vol. 51, no. 9, pp. 1665-1674, Sept. 2004.
[4] T. D. Loveless, et al., "A generalized linear model for single event transient propagation in phase-locked loops," IEEE Trans. on Nuclear Science, vol. 57, no. 5, pp. 2933-2947, Oct. 2010.
[5] H. Adrang and H. M. Naimi, "A novel method for analysis and design of third-order charge pump PLL," in Proc. IEEE European Conf. on Circuit Theory and Design, ECCTD’09, pp. 591-594, Antalya, Turkey, 23-27 Aug. 2009.
[6] L. A. H. Monterio, D. N. Favaretto Filho, and J. R. C. Piqueira, "Bifurcation analysis for third-order phased-locked loops," IEEE Signal Processing Letters, vol. 1, no. 5, pp. 494-496, May 2004.
[7] H. Dehbovid, H. Adarang, and M. B. Tavakoli, "Nonlinear analysis of VCO jitter generation using volterra series," The International J. for Computation and Mathematics in Electrical and Electronic Engineering, vol. 37, no. 2, pp. 755-771, Mar. 2018.
[8] A. Carlosena, M. Ugarte, and A. J. Lopez-Martin, "Loop filter approximation for PLLs," in Proc. 51st Midwest Symp. on Circuits and Systems, pp. 21-24, Knoxville, TN, USA, 10-13 Aug. 2008.
[9] A. Carlosena and A. M. Lazaro, "A novel design method for phased-locked loops of any order and type," in Proc. 49th IEEE Int. Midwest Symp. on Circuits and Systems, vol. 2, pp. 569-573, San Juan, PR, USA, 6-9 Aug. 2006.
[10] Y. F. Kuo, R. M. Weng, and C. Y. Liu, "A fast locking PLL with phase error detector," in Proc. IEEE Conf. on Electron Devices and Solid-State Circuits, pp. 423-426, Hong Kong, China, 19-21 Dec. 2005.
[11] S. Liu and Y. Shi, "Fast locking and high accurate current matching phase-locked loop," in Proc. IEEE Asia Pacific Conf. on Circuits and Systems, pp. 1136-1139, Macao, China, 30 Nov.-3 Dec. 2008.
[12] M. Mansuri and C. K. Ken Yang, "A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation," IEEE J. of Solid-State Circuits, vol. 38, no. 11, pp. 1804-1812, Nov. 2003.
[13] W. H. Chiu, Y. H. Huang, and T. H. Lin, "A dynamic phase error compensation technique for fast-locking phase-locked loops," IEEE J. of Solid-State Circuits, vol. 45, no. 6, pp. 1137-1149, Jun. 2010.
[14] V. S. Sadeghi and H. Miar-Naimi, "A new fast locking charge pump PLL: analysis and design," Analog Integrated Circuits and Signal Processing, vol. 74, pp. 569-575, Jan. 2013.
[15] V. S. Sadeghi and H. Miar-Naimi, "A new frequency comparator for using in fast charge pump PLLs," in Poc. 21st Iranian Conf. on Electrical Engineering, ICEE’13, 3 pp., Mashhad, Iran, 14-16 May 2013.
[16] ها. ده¬بوید، ح. آدرنگ و م. ب. توکلی، "تحلیل غیر خطی جیتر انتقالی در حلقه قفل فاز پمپ بار با استفاده از بسط سری ولترا،" نشریه مهندسی برق و مهندسی كامپیوتر ایران، الف- مهندسی برق، سال 16، شماره 2-الف، تابستان 1397.
[17] K. Zhu, V. Saxena, X. Wu, and S. Balagopal, "Design analysis of a 12.5 GHz PLL in 130 nm SiGe BiCMOS process," in Poc. IEEE Workshop on Microelectrnics and Electron Device, 4 pp., Boise, ID, USA, 20-20 Mar. 2015.