CMOS Low-Dropout Voltage Regulator with Controlled Pass Transistor
Subject Areas : electrical and computer engineering
F.
Qaraqanabadi
1
A.
Saberkari
2
Keywords: Low-dropout regulator (LDO) pass transistor power management quiescent current,
Abstract :
This paper presents a low quiescent current low-dropout voltage regulator (LDO) with controlled pass transistor which can work either with on-chip or off-chip output capacitor. The pass transistor of the proposed LDO has lower width in low load condition and has higher width for moderate to heavy load current and the LDO topology transforms between a two-stage structure in low load current and a three-stage one in moderate to high load current. The proposed LDO topology is designed and simulated in HSPICE in a 0.35 µm CMOS process to provide a 2.8 V output voltage for a 3 V input voltage and is capable to deliver a stable output current in the range of 0-100 mA to the load with a 100 pF on-chip output capacitor while its quiescent current is only 7.5 µA. Without using the adaptively-controlled pass transistor, the maximum output variations of the LDO to the 0-100 mA load transient is 540 mV and its settling time is 11 µs, while using this technique decreases the output voltage variations and settling time to 280 mV and 6.5 µs, respectively.
[1] D. D. Buss, "Technology in the interest age," in Proc. IEEE Int. Solid - State Circuits Conf., ISSCC'02, vol. 1, pp. 18-21, Feb. 2002.
[2] R. Fathipour and A. Saberkari, "FVF - based CMOS low - dropout regulator," J. Electronics Industries, vol. 3, no. 3, pp. 7-24, Aug. 2013
[3] A. Saberkari, E. Alarcon, and S. B. Shokouhi, "Fast transient current-steering CMOS LDO regulator based on current feedback amplifier," Integration, the VLSI J., vol. 46, no. 2, pp. 165-171, Mar. 2013.
[4] R. J. Milliken, J. Silva - Martinez, and E. Sanchez - Sinencio, "Full on - chip CMOS low - dropout voltage regulator," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 54, no. 9, pp. 1879-1890, Sep. 2007.
[5] K. L. Leung and P. K. T. Mok, "A capacitor - free CMOS low - dropout regulator with damping-factor-control frequency compensation," IEEE J. Solid - State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003.
[6] T. Y. Man, K. L. Leung, C. Y. Leung, P. K. T. Mok, and M. Chan, "Development of single - transistor - control LDO based on flipped voltage follower for SOC," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 55, no. 5, pp. 1392-1401, Jun. 2008.
[7] Y. H. Lam and W. H. Ki, "A 0.9 V 0.35 µm adaptively biased CMOS LDO regulator with fast transient response," in Proc. IEEE Int. Solid - State Circuits Conf., ISSCC'08, pp. 442-443, 3-7 Feb. 2008.
[8] M. Al - Shyoukh, H. Lee, and R. Perez, "A transient - enhanced low -quiescent current low - dropout regulator with buffer impedance attenuation," IEEE J. Solid - State Circuits, vol. 42, no. 8, pp. 1732-1742, Aug. 2007.
[9] Y. H. Lam, W. H. Ki, and C. Y. Tsui, "Adaptively - biased capacitor - less CMOS low dropout regulator with direct current feedback," in Proc. IEEE Asia South Pacific Conf. Design Automation, pp. 104-105, 24-27 Jan. 2006.
[10] R. Fathipour and A. Saberkari, "Capacitor - free CMOS low - dropout regulator with a fast path embedded into the error amplifier," Iranian J. Electrical Computer Engineering, vol. 11, no. 2(a), pp. 105-111, Dec. 2013.
[11] W. J. Huang and S. I. Liu, "Capacitor - free low dropout regulators using nested miller compensation with active resistor and 1 - bit programmable capacitor array," IET Circuits Devices Syst., vol. 2, no. 3, pp. 306-316, Jun. 2008.
[12] Y. L. Lo and W. J. Chen, "A 0.7 V input output - capacitor - free digitally controlled low-dropout regulator with high current efficiency in 0.35 µm CMOS technology," Microelectronics J., vol. 43, no. 62, pp. 756-765, Aug. 2012.
[13] P. Hazucha, T. Karnik, B. Bloechel, C. Parsons, D. Finan, and S. Borkar, "Area - efficient linear regulator with ultra - fast load regulation," IEEE J. Solid - State Circuits, vol. 40, no. 4, pp. 933-940, Apr. 2005.