Design of 15-Bit 12-MHz Nyquist Bandwidth 5th-Order Single Stage Sigma-Delta Modulator
Subject Areas : electrical and computer engineering
1 - Tarbiat Modares University
2 -
Keywords: IIR filter low-distortion noise transfer function sigma-delta modulator,
Abstract :
In this paper a 5th-Order single-loop Sigma-Delta Modulator with low distortion structure is presented. This structure, which uses integrator and IIR filter concurrently, has relatively less feedforward paths and modulator coefficients. Thus, its sensitivity to coefficient mismatching is reduced. To lower the power consumption of the modulator, the 2-order IIR filter block is implemented by single OTA, and a passive adder is used to realize input quantizer adder. Simulation results show that this structure can achieve 15-bit of resolution and 6 MHz input signal bandwidth, with 1.2 V supply voltage using a 0.13 µm CMOS technology. Power consumption of modulator is 53 mW. Comparing with other structures, the proposed modulator has higher performance because of increasing the DR and input bandwidth of modulator without extra increasing the power consumption.
[1] R. Schreier and G. C. Temes, Understanding Delta - Sigma Data Converters, Wiley/IEEE Press, 2005.
[2] M. Safi-Harb and G. W. Roberts, "Low power delta-sigma modulator for ADSL applications in a low-voltage CMOS technology," IEEE Trans. on Circuits System I, vol. 52, no. 10, pp. 2075-2089, Oct. 2005.
[3] R. Jiang and T. Fiez, "A 14bit delta-sigma ADC with 8x OSR and 4 MHz conversion bandwidth in a 0.18um CMOS process," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 63-74, Jan. 2004.
[4] M. Yavari, O. Shoaei, and A. Rodriguez-Vazquez, "Double-sampling single-loop sigma delta modulator topologies for broad-and applications," IEEE Trans., vol. 53, no. 4, pp. 314-318, Apr. 2006.
[5] K. Nam, S. Lee, D. Su, and A. Wooley, "A low-voltage low-power sigma - delta modulator for broadband analog - to - digital conversion," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1855-1864, Sep. 2005.
[6] J. Silva, U. Moon, J. Steensgaard, and G. Temes, "Wideband low distortion delta - sigma ADC topology," Electronics Letters, vol. 37, no. 12, pp. 737-738, Jun. 2001.
[7] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto, and F. Maloberti, "Modeling sigma-delta modulator non idealities in SIMULINK," in Proc. IEEE Int. Symp. on Circuits and Systems, ISCAS'99, vol. 2, pp. 384-387, Orlando, US, 30 May-2 Jun. 1999.
[8] G. Suarez, M. Jimenez, and F. O. Fernandez, "Behavioral modeling methods for switched - capacitor ΣΔ modulators," IEEE Trans. on Circuits and Systems I, vol. 54, no. 6, pp. 1236-1244, Jun. 2007.
[9] A. Safarian, F. Sahandi, and S. Atarodi, "A new low-power delta-sigma modulator with the reduced number of op-amps for speech band applications," in Proc. IEEE Int. Symp. on Circuits and Systems, ISCAS'03 vol. 1, pp. 1033-1036, Bangkok, Thailand, 25-28 May 2003.
[10] P. Balmelli and Q. Huang, "A 25-MS/s 14-b 200-mW sigma delta modulator in 0.18um CMOS," IEEE J. of Solid - State Circuits, vol. 39, no. 12, pp. 2161-2170, Dec. 2004.
[11] M. Yavari and O. Shoaei, "Hybrid cascade compensation for two-stage CMOS opamps," IEICE Trans. on Electronics, vol. 88, no. 3, pp. 1161-1165, Jun. 2005.
[12] S. Rabii and B. A. Wooley, The Design of Low - Voltage, Low - Power Sigma-Delta Modulators, Kluwer Academic Publisher, Boston, 1999.
[13] M. Taghizadeh, A. Nabavi, and D. Mahmoodi, "A 15 bits 12 MS/s 5th-order sigma-delta modulator for communication applications," in Proc. Int. Conf. on Microelectronics, ICM2008, pp. 408-411, Sharjah, UAE, Dec. 2008.