جمعکننده نافرار و توان پایین مبتنی بر فناوری اسپینترونیک برای پیادهسازی محاسبات در حافظه
محورهای موضوعی : مهندسی برق و کامپیوترعبداله امیرانی 1 , کیان جعفری 2 * , رامین رجایی 3
1 - دانشگاه شهید بهشتی
2 - دانشگاه شهید بهشتی
3 - دانشگاه شهید بهشتی
کلید واژه: پیوند تونل مغناطیسیطراحی توان پایینفناوری اسپینترونیکمحاسبات در حافظهمدارهای ترکیبی MTJ/CMOS,
چکیده مقاله :
با پیشرفت فناوری و کوچکشدن اندازه ترانزیستورها به خصوص در فناوریهای زیر 90 نانومتر مصرف توان ایستای بالا به علت افزایش نمایی جریان نشتی ترانزیستورها به یکی از بزرگترین مشکلات مدارهای مبتنی بر فناوری CMOS تبدیل شده است. افزارههای اسپینترونیک مانند پیوند تونل مغناطیسی (MTJ) با توجه به ویژگیهای منحصربهفردشان از جمله مصرف توان ایستای پایین، نافراربودن، طول عمر زیاد، سازگاری با ترانزیستورهای CMOS و امکان ساخت در چگالیهای بالا یکی از گزینههای مورد توجه برای طراحی مدارهای ترکیبی MTJ/CMOS و غلبه بر معضل مصرف توان ایستای بالا در مدارهای مبتنی بر فناوری CMOS است. در این مقاله یک تمام جمعکننده ترکیبی MTJ/CMOS کاملاً نافرار و توان پایین برای پیادهسازی محاسبات در حافظه ارائه شده است. نتایج شبیهسازیها نشان میدهد که تمام جمعکننده نافرار پیشنهادی نسبت به تمام جمعکنندههای نافرار موجود حداقل 50 درصد سریعتر بوده، حاصلضرب توان در تاخیر آن 39 درصد کمتر است و سربار سختافزاری زیادی نیز به مدار تحمیل نمیکند.
As technology nodes shrink below 90 nm, high static power consumption has become one of the biggest problems of CMOS based circuits due to the exponential leakage current of transistors. Spintronic devices such as magnetic tunnel junction (MTJ) due to their fascinating features such as low static power consumption, non-volatility, high endurance, compatibility with CMOS transistors and high-density fabrication are one of the promising candidate for designing hybrid MTJ/CMOS circuits and overcoming high static power consumption of CMOS based circuits. In this paper, a fully nonvolatile and low power hybrid MTJ/CMOS full-adder circuit for Realization of Process in Memory is proposed. The simulation results show that all the proposed circuit is at least 50% faster than all previous counterparts, the power output delay is 39% lower than the previous design, and does not impose high hardware overhead.
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